1. Field of the Invention
The field of the invention relates to integrated circuits and in particular to supplying power to the integrated circuits.
2. Description of the Prior Art
With advances in semiconductor technology, semiconductor chips are getting ever smaller and a limiting factor to the decrease in the size of the device is now often the size of the area required to bond a wire to the device so that external signals and power can be supplied to the device. Such chips are termed pad limited and over 90% of chips now fall within this category.
The minimum width of the area required to bond a wire to a device is termed the pitch of the device. When supplying power to a semiconductor core a power pad is used to provide a connection between the wire bonded to the device and the core. Cores need to be protected from electrostatic discharge which can cause surge currents and local heating of the device, and this is done using ESD (electrostatic discharge) clamps within the power pads that are supplying the power.
These power pads or power cells have metal strips that connect the power line bonded to the outside of the power pad to the core. However, in order to provide the required ESD protection these metal strips are also used to provide connections to the ESD clamps. FIG. 1a shows the metal strips of a power pad of the prior art, FIG. 1b shows a circuit diagram of a VDD power pad of the prior art, and FIG. 1c shows a cross section of this power pad.
As can be seen from FIG. 1c on the top there is a bonding layer 10 where a metal wire 8 is bonded to the power pad, then in the next layer there are the power rails of the integrated circuit that run around the edge of the integrated circuit. These are shown schematically as being arranged one on top of the other, but are in reality arranged side by side. Power rail 12 is connected to VSS at least one other power cell via a wire bonded to this cell at bonding layer 10, and power rail 14 is connected to VDD via wire 8 at this power cell and possibly at other power cells too. There is then the metallisation layer comprising metal strips 16 (shown in FIG. 1a). Some of these metal strips are connected to VDD via the bonding layer and take the power from this layer to the core of the integrated circuit. Only half of the metal strips of this layer are connected to VDD however, the other half are connected to the VSS rail and are used for electrostatic discharge protection. Thus, the ESD clamp 18, which in this embodiment is a large transistor in the lower layers is connected between VSS and VDD via the metal rails of the metallisation layer 16 and this large transistor provides a power surge current path to protect the integrated circuit.
As noted above as devices are getting smaller they are becoming limited by the pitch of the device and this is determined by the width required to bond a wire. Furthermore, as this gets smaller, the metal strips in the metallisation layer 16 for supplying current to the cell also need to get correspondingly smaller, thereby restricting the amount of current that can be supplied. It would be desirable to be able supply more current to a core without increasing the number of power pads.